P89LPC952 NXP Microcontroller User Manual

Description

This PDF user manual is for the NXP P89LPC952 microcontroller.

NXP P89LPC952 Microcontroller

Technical information for the P89LPC952 device.

The P89LPC952 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC952 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices.

(PDF) USER MANUAL (ENGLISH)

CONTENTS

1. Introduction
1.1 Pin configuration
1.2 Pin description
1.3 Special function registers
1.4 Memory organization

2. Clocks
2.1 Enhanced CPU
2.2 Clock definitions. Oscillator Clock (OSCCLK). Low speed oscillator option. Medium speed oscillator option. High speed oscillator option.
2.3 Clock output
2.4 On-chip RC oscillator option
2.5 Watchdog oscillator option
2.6 External clock input option
2.7 Oscillator Clock (OSCCLK) wake-up delay
2.8 CPU Clock (CCLK) modification: DIVM register
2.9 Low power select

3. A/D converter
3.1 General description
3.2 A/D features
3.2.1 A/D operating modes: Fixed channel, single conversion mode/continuous conversion mode; Auto scan, single conversion mode/continuous conversion mode; Dual channel, continuous conversion mode; Single step mode.
3.2.2 Conversion mode selection bits
3.2.3 Conversion start modes: Timer triggered start; Start immediately; Edge triggered.
3.2.4 Stopping and restarting conversions
3.2.5 Boundary limits interrupt
3.2.6 Clock divider
3.2.7 I/O pins used with ADC functions
3.2.8 Power-down and Idle mode

4. Interrupts
4.1 Interrupt priority structure
4.2 External Interrupt pin glitch suppression

5. I/O ports
5.1 Port configurations
5.2 Quasi-bidirectional output configuration
5.3 Open drain output configuration
5.4 Input-only configuration
5.5 Push-pull output configuration
5.6 Port 0 and Analog Comparator functions
5.7 Additional port features

6. Power monitoring functions
6.1 Brownout detection
6.2 Power-on detection
6.3 Power reduction modes

7. Reset
7.1 Reset vector

8. Timers 0 and 1
8.1 Mode 0
8.2 Mode 1
8.3 Mode 2
8.4 Mode 3
8.5 Mode 6
8.6 Timer overflow toggle output

9. Real-time clock system timer
9.1 Real-time clock source
9.2 Changing RTCS1/RTCS0
9.3 Real-time clock interrupt/wake-up
9.4 Reset sources affecting the Real-time clock

10. UARTs
10.1 Mode 0
10.2 Mode 1
10.3 Mode 2
10.4 Mode 3
10.5 SFR space
10.6 Baud Rate generator and selection
10.7 Updating the BRGR1 and BRGR0 SFRs
10.8 Framing error
10.9 Break detect
10.10 More about UART Mode 0
10.11 More about UART Mode 1
10.12 More about UART Modes 2 and 3
10.13 Framing error and RI_n in Modes 2 and 3 with SM2_n = 1
10.14 Break detect
10.15 Double buffering
10.16 Double buffering in different modes
10.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)
10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)
10.19 Multiprocessor communications
10.20 Automatic address recognition

11. I2C interface
11.1 I2C data register
11.2 I2C slave address register
11.3 I2C control register
11.4 I2C Status register
11.5 I2C SCL duty cycle registers I2SCLH and I2SCLL
11.6 I2C operation modes: Master Transmitter mode; Master Receiver mode; Slave Receiver mode; Slave Transmitter mode.

12. Serial Peripheral Interface (SPI)
12.1 Configuring the SPI
12.2 Additional considerations for a slave
12.3 Additional considerations for a master
12.4 Mode change on SS
12.5 Write collision
12.6 Data mode
12.7 SPI clock prescaler select

13. Analog comparators
13.1 Comparator configuration
13.2 Internal reference voltage
13.3 Comparator input pins
13.4 Comparator interrupt
13.5 Comparators and power reduction modes
13.6 Comparators configuration example

14. Keypad interrupt (KBI)

15. Watchdog timer (WDT)
15.1 Watchdog function
15.2 Feed sequence
15.3 Watchdog clock source
15.4 Watchdog Timer in Timer mode
15.5 Power-down operation
15.6 Periodic wake-up from power-down without an external oscillator

16. Additional features
16.1 Software reset
16.2 Dual Data Pointers
16.3 Debugger interface
16.3.1 Debugger connections

17. Flash memory
17.1 General description
17.2 Features
17.3 Flash programming and erase
17.4 Using Flash as data storage: IAP-Lite
17.5 In-circuit programming (ICP)
17.6 ISP and IAP capabilities of the P89LPC952/954
17.7 Boot ROM
17.8 Power on reset code execution
17.9 Hardware activation of Boot Loader
17.10 In-system programming (ISP)
17.11 Using the In-system programming (ISP)
17.12 In-application programming (IAP)
17.13 IAP authorization key
17.14 Flash write enable
17.15 Configuration byte protection
17.16 IAP error status
17.17 User configuration bytes
17.18 User security bytes
17.19 Boot Vector register
17.20 Boot status register

18. Instruction set

19. Legal information
19.1 Definitions
19.2 Disclaimers
19.3 Trademarks

20. Tables

21. Figures

22. Contents

Why download the Manual?

This user manual provides all the information from NXP about the P89LPC952 microcontroller, as detailed in the table of contents. Reading it completely will address most questions you might have. You can download and save it for offline use, including viewing it on your device or printing it for your convenience if you prefer a paper version.

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